DeepX Tapes Out DX-M2 Edge AI Chip for 100B Parameter LLMs at 5 W

Details

DeepX has taped out the DX-M2, a second-generation edge AI accelerator designed to run LLMs with up to 100 billion parameters at less than 5 W.
The chip targets 20B to 100B parameter models (3B to 20B active parameters) with inference speeds of 10 to 30 tokens per second.
Simulations show that offloading GEMV operations to Samsung's LPDDR5x-PIM yields a 6.7x increase in tokens per second for Llama3.1-8B, though this requires 2.7x the power consumption.
Memory bandwidth triples from 50 GB/s to 150 GB/s, and the move to a 2-nm process node doubles NPU power efficiency to achieve 80 TOPS.
Samples are expected in March 2027, with mass production targeted for fall 2027.
The DX-M3 is planned for 2028, featuring a chiplet-based design and support for LPDDR6-PIM to target automotive and humanoid robotics markets.
DeepX is developing the DX-Newton software stack to allow robotics customers to migrate from Nvidia Isaac with a simple API change, claiming 20 times longer battery life.

Key point