Tensor Contraction Processor: AI Chip Architecture

AI hardware must simultaneously achieve high programmability and power efficiency to meet explosive computational demand. However, existing GPUs have limitations: they are difficult to optimize as models change, and they consume massive power exceeding 1,000W per chip.

To solve this, FuriosaAI developed the Tensor Contraction Processor (TCP) architecture. TCP is designed around core AI operations, efficiently managing data and memory, and powers high-performance generative AI models like Llama 3 through its next-generation chip, RNGD (Renegade).

TCP is co-designed with the software stack to provide high programmability. In particular, through a universal compiler that processes the entire model as a single fused operation, even models with new architectures can be automatically optimized and deployed.

Data movement consumes up to 10,000 times more energy than the computation itself. TCP maximizes energy efficiency by reusing data stored in on-chip memory to minimize data movement. RNGD is scheduled for release later this year.