AMD GFX1250 LLVM Tea Leaves Analysis

By analyzing commit history in the LLVM project, the detailed specifications of AMD's next-generation data center accelerator, the MI400 series, have been inferred.

The main subject of analysis, GFX1250 (MI455X), is a chip targeting the machine learning market and is expected to be mounted in Helios racks. Meanwhile, GFX1251 (MI430X) targets the HPC market and is expected to deliver over 200 TFLOPs of FP64 (Double-precision) compute performance.

Key architectural features of GFX1250:

• Wave32 mode only: Unlike existing CDNA, it operates only in Wave32 mode, which may hint at future changes in AMD's GPU architecture.
• WMMA support: Supports WMMA (Warp Matrix Multiply-Accumulate) instead of the existing MFMA, strengthening machine learning computation capability.
• Improved register file: Each Wave can address up to 1024 VGPRs (Vector General Purpose Registers) in the register file, a significant improvement over the previous generation (up to 512).
• WGP structure change: The cache hierarchy has been unified to the point where the distinction between CUs (Compute Units) within a WGP (Workgroup Processor) becomes meaningless from a compiler perspective.