Anatomy of SSD Internal Structure: Page/Block Operations and FTL Logical Mapping Principles

NAND flash memory does not allow access to specific cells individually; reads and writes are executed only in Page units, while erases are executed only in Block units. Pages cannot be overwritten, so modifying data requires a Read-Modify-Write process where existing data is read, modified, and written to a new page. The unnecessary additional writes generated during this process are called Write Amplification, which directly impacts SSD lifespan and performance.

The Role of FTL and Logical Block Mapping

The FTL (Flash Translation Layer) inside the SSD controller is a core component that translates the host's Logical Block Addresses (LBA) into the NAND's Physical Block Addresses (PBA). The primary purposes of the FTL are logical block mapping and Garbage Collection. Mapping methods include page-level, block-level, and a compromise known as Hybrid Log Block Mapping. The Hybrid method reduces Write Amplification by converting random writes into sequential writes, and improves efficiency by merging or switching log blocks with data blocks when they become full.

Wear Leveling and Garbage Collection

NAND cells have limited P/E Cycles (Program/Erase Cycles), so excessive use of specific blocks shortens their lifespan. The FTL performs Wear Leveling to evenly distribute wear across all blocks. Additionally, it performs Garbage Collection, which erases blocks at the block level to reuse deleted pages. Since background Garbage Collection can impact write performance, separating and managing Hot data and Cold data, and caching frequently changed data, is key to performance optimization.