Making RAM at Home [video]

A DRAM cell was fabricated using home equipment and a self-built process, confirming the operation of the basic RAM structure consisting of a transistor and a capacitor.

• The goal was a device that could later be scaled into a 5x4 array, with a transistor and storage capacitor placed at each intersection point.
• After cutting a silicon wafer, an oxidation process at 1100°C produced an oxide layer of about 3300 angstroms, followed in sequence by photolithography, dry etching, doping, gate oxide growth, contact cuts, and aluminum deposition.
• Source and drain regions were formed using phosphorus doping and phosphorus doped spin-on glass, after which a 950°C, 38 minute process grew a gate/capacitor oxide layer of about 200 angstroms (20nm).
• The finished device showed switching characteristics where current varied with gate voltage, and the capacitor recorded a maximum of 12.3 pF.
• In individual cell operation, the storage capacitor could be charged to 3V within a few hundred nanoseconds, but the charge was retained for just over 2ms before requiring a recharge.
• This fell short of commercial DRAM's 64ms-level retention time, and short channel effects such as punch through also appeared due to the short source-drain distance.

As a result, the home-built small-scale DRAM is still at the level of just a few cells, but it provides a starting point that could be expanded into a larger array by adding read and refresh circuitry.