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Qwenputer embeds RISC-V CPU by converting GDN state to RAM

·2026.11.01 17:00

Key point

Qwenputer, an experimental model adding a RISC-V CPU to Qwen3.5-4B, is released, recording 97.5% accuracy on synthetic arithmetic benchmarks

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Details

  • Qwenputer, an experimental model with 11 layers of a 32-bit RISC-V CPU (RV32IM) attached before Qwen3.5-4B, is released
  • Gated DeltaNet (GDN) state is utilized as RAM to implement CPU memory within the model weights
  • Recorded 97.5% accuracy on synthetic integer arithmetic benchmarks compared to 75.0% for base Qwen, achieving 97.5–100% on the DeepMind arithmetic set
  • Verified improved persistent memory storage and recall performance across conversations using an experimental file system
  • Checkpoint size is 18.8GB, requiring one 24GB GPU, with code under MIT license and weights under Apache-2.0
  • Execution of MicroPython merged into the model is incomplete, with development planned for stage P4
risc-vllm-architecturegated-deltanetqwenputerexperimental-modeldivyansh-agrawal
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