AI Briefing#risc-v
The latest AI and developer news about #risc-v, with the original source and a short summary.
The latest AI and developer news about #risc-v, with the original source and a short summary.
Qwenputer, an experimental model adding a RISC-V CPU to Qwen3.5-4B, is released, recording 97.5% accuracy on synthetic arithmetic benchmarks
The joint research generated approximately 180 million lines of Rocq proof code to verify RISC-V assembly-level security for 239 entry points, discovering bugs that fuzzers missed.
Basis Research used LLMs to write formal semantics for an extended WHILE language and prove in Lean that its compiled C interpreter's RISC-V binary execution matches those semantics.
Magnetar proves RISC-V execution at 7.2 to 8.7 million instructions per second on a laptop using only standard hash functions.
Google combined Antigravity's Teamwork framework with Gemini 3.7 Flash to solve complex multi-agent problems.
Nvidia has disclosed the hardware requirements for running CUDA on RISC-V server CPUs.
Meta improved inference efficiency by reusing old DDR4 memory in new server infrastructure through 'Vistara,' a custom CXL ASIC.
ByteDance is starting development of its own CPU to bolster AI infrastructure support and address processor supply delay issues.
A 12.6M-parameter DCGAN was implemented in pure C on a RISC-V microcontroller with 512KB of SRAM.
Sipeed unveiled the K3 RISC-V SBC series, touting 60 TOPS and 30B LLM operation.
AI-based chip design startup Cognichip has raised $60 million in new funding, aiming to cut design costs by 75% and shorten development time.