AI BriefingTSMC Demonstrates 1T1C Oxide Semiconductor Memory Integrated into Logic Chip BEOL
·2026.11.07 22:17
Key point
The technology operates at 0.75V with data retention exceeding 128ms, targeting high-density processor caches with lower power consumption than SRAM.
Details
- TSMC presented a 1T1C oxide semiconductor memory technology at the 2025 VLSI Symposium, designed to integrate memory directly into the back end of line (BEOL) interconnect layers of advanced logic chips.
- Test chip results show operation at 0.75V, data retention exceeding 128ms, random read/write cycle time under 8ns, and endurance above 10^14 cycles.
- The design uses oxide semiconductor channel transistors and low-temperature process capacitors to enable memory integration within logic die interconnects, unlike conventional separate DRAM chips.
- TSMC positions the technology as a processor cache offering higher density than SRAM while maintaining low power and latency.
- The company is also exploring 3D DRAM production, which would place it in competition with Samsung, SK Hynix, and Micron.
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